scan-chain

SPM with DFT structure automatically injected by Fault

VHDL circuit testing project featuring scan-based TRCUT architecture with testbenches, LFSR-based pseudorandom input generation, MISR-based signature analysis with fault injection (stuck-at and transient), and full IEEE 1149.1 (JTAG) implementation with TAP controller and boundary scan.

Post-manufacturing test analysis

Design, verification, synthesis, and ATPG analysis of a Verilog FSM traffic controller with BIST. 90.93% fault coverage, 144.7 µm² area, 68.6 µW total power. Built with Synopsys DC + TetraMAX on the Nangate 45nm Open Cell Library.

A comprehensive Verilog implementation of modern hardware testing architectures, featuring DFT (Scan Chains), BIST (LFSR/MISR), and the IEEE 1149.1 JTAG standard.

Research framework for physical- and ATPG-aware scan-architecture co-optimization, with routed validation and documented negative physical-impact results.

Scan insertion and stitching, so a chip can be tested after fabrication.

Two 7-bit scan chains in Verilog, one locked with key bits, showing what scan obfuscation hides and what it leaks

ATPG from scratch in C++ (D-Algorithm, PODEM, fault sim, BIST, scan) with PPA-aware test point insertion

Quick and Dirty conservative scan-chain structural audit

Sustained fault injection for RISC-V over the DFT scan chain — flip bits in real FFs at any cycle while the processor runs

VLSI testing and design-for-testability in SystemVerilog: stuck-at fault models, serial fault simulation, an LFSR test-pattern generator and a 4-bit scan chain.

Find DFT problems before they become expensive scan-insertion and ATPG problems.