We recently had an issue where the "old" mic array dual API started exhibiting noise when run at 800MHz.
Typical mics (eg. infineon) have a clock to data valid of up to 80ns (a lot, and approx quarter of a 3MHz clock cycle) so just setting set_port_sample_delay() makes sense. Doing this causes the PDM mic mapping to revert from 0->1 1->0 (swapped) to 0->0 1->1
For DDR we also manually align the capture clock and PDM output clock using an outpw.
I suggest that we take the time to simulate the timing of mic capture for SDR and especially DDR to verfiy that the original design meets timing as expected.
Ideally this will be part of the test regression than a one - off. It should be possible in xsim
We recently had an issue where the "old" mic array dual API started exhibiting noise when run at 800MHz.
Typical mics (eg. infineon) have a clock to data valid of up to 80ns (a lot, and approx quarter of a 3MHz clock cycle) so just setting set_port_sample_delay() makes sense. Doing this causes the PDM mic mapping to revert from 0->1 1->0 (swapped) to 0->0 1->1
For DDR we also manually align the capture clock and PDM output clock using an outpw.
I suggest that we take the time to simulate the timing of mic capture for SDR and especially DDR to verfiy that the original design meets timing as expected.
Ideally this will be part of the test regression than a one - off. It should be possible in xsim