gate-level

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

Customizable fault-simulation and gate-level editing library for sequential circuits

This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022

Gate-level circuit model for ROSS

TrojanWars🐎 - Test Generation for activation of malicious hardware implants

implement mips cpu in python

FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)

Gate-level carry-lookahead adders in the dual product-of-sums form, 2421 decimal adders and hazard-free two-level logic. SAT proofs over all 2^33 inputs, transport-delay timing checked against hand derivations, and an automated static-hazard glitch scan. Pinned-toolchain CI.

Doom running on a RISC-V CPU (FemtoRV32 Electron, RV32IM) built by hand from 13,607 logic gates in SHDL

End-to-end framework to bridge gate-level hardware stuck-at faults and application-level software degradation in INT8/UINT8 Quantized Neural Networks.

Реализация элементов цифровых схем из базовых логических элементов

Area-efficient approximate comparators (4–32 bit) with Verilog RTL, testbenches, and analysis.

USAGI is a Python script designed to automate the process of synthesizing and performing gate-level simulations for digital designs across a range of cycle times.

Static glitch/hazard analysis: a gate-level netlist + Liberty in, reconvergent-fanout hazards out.