A synthesizable 16-stage pipelined CORDIC engine in Verilog for high-throughput sine and cosine calculation. 🚀
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Updated
Mar 24, 2026 - Verilog
A synthesizable 16-stage pipelined CORDIC engine in Verilog for high-throughput sine and cosine calculation. 🚀
Self-checking ALU Verification using SystemVerilog, Functional Coverage and Scoreboard
A universal decentralized trust layer for independently verifying digital information across Education, Supply Chain, Legal Evidence, and Cybersecurity.
FPGA programmable delay logic portfolio covering a shift-register baseline, circular-queue PPA analysis, and memory-based file-driven verification.
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