Library704

Verilog simulation of an IBM 704

The goal of this project is to have cycle and logic exact simulaton of an IBM 704 based on the existing schematics from the bitsavers IBM704 directory. See http://www.bitsavers.org/pdf/ibm/704/ (Files 704_schemVol1.pdf 704_schemVol2.pdf 704_schemVol4.pdf)

The diagrams are stored here as textfiles in a custom netlist-like-format and then converted into Verilog by the C# program. (for a syntax description see the comments of file "Program.cs")

Current state:

• The IBM 704 CPU with all instructions, core ,emory and operators panel lights/buttons/swichtes are working.
• Cardreader, printer and punch similations exsits which reads/writes the data via Verilog file I/O.
• No Tape and Drum simulation.
• Some diagrams are missing in the existing schematics. These were rebuild from the context and from the other existing IBM 704 documents.
• The generated verilog file runs only in Icarus Verilog.
• The simulaton is very slow.

Instructions:

1. Install Icarus Verilog from here http://bleyer.org/icarus/ Perform full installation (includes GTKWave) Select "Add executable folder(s) to the user PATH" during install.

2. Clone or download this project. It can be opened in Visual Studio, or built from the command line with the .NET SDK - the project is an SDK style project targeting net10.0, so it works on Windows and on Linux alike.

3. Run the converter. It takes the folder containing the *.txt schematic files, plus options.

   dotnet run --project Library704 -- Library704

   It reads all *.txt module files from that folder, converts them into verilog and writes them into a single file I704.v located in subfolder "Testbench" of that same folder.

   Options, before or after the folder:

   --multiple-files write one .v file per module into "Testbench/gen" instead of the single I704.v. Easier to read while debugging. Use it with exactly one testbench: iverilog -o Sort.vvp gen/*.v system_tb_sort.v && vvp Sort.vvp A plain "iverilog *.v" in the Testbench folder fails, because both system_tb_sort.v and system_tb_LOAD_CR.v define the module SYSTEM_tb. Every file in gen is rewritten, so leftovers of a renamed module are deleted before the run, and each file is only put in place once it is complete. --print-busses add a comment block for every wired-or/wired-and bus to the generated Verilog, listing the pins that read and drive it. Only useful while looking for a wiring problem, it makes the output considerably longer. --parts print after conversion how often each circuit element appears in the schematics.

   The program exits with 0 only when it reported no error. Reported problems are on stderr and prefixed with error: or warning:, so the conversion progress on stdout stays readable. In Visual Studio this is already set up, F5 is enough: Properties\launchSettings.json passes "." as the argument, which is the project folder holding the *.txt files. From the command line the argument is resolved against the current directory, so either run "dotnet run" inside the project folder, or use the explicit form above. This step has to be repeated whenever a schematic changed, because I704.v itself is not stored in git.

4. Open windows explorer and browse into subfolder Testbench. On Linux run ./Sort.sh and ./LOAD_CR.sh from that folder instead, they do the same as the .cmd files.

5. Double click on Sort.cmd

   This will run Icarus verilog with the generated I704.v and the testbench file system_tb_sort.v.

   The testbench writes a short bubble-sort program into the memory and then pressed the start button. (from "Coding_for_the_MIT-IBM_704_Computer_Oct57.pdf" page 54)

   The program runs for a few seconds. Then GTK Wave is openend with the simulation result.

   In gtkwave you see then main machine cycles states and the registers as shown at the operators panel.

   I-Time= instruction fetch/decoding.
   E-Time= instruction execution with core memory access.
   ER-Time= instruction execution without core memory access

   The entries A1-A10 are the memory cells that are sorted.

6. Close Gtkwave and double click on LOAD_CR.cmd. This runs the testbench system_tb_LOAD_CR.v. It presses the "Load Card" button of the machine. Then the simulated IBM 704 boots from the cardreader the file "CRD.cbn" (This is a small HELLO WORLD program generated with the UASAP assembler and the UASPH1 routine from the share tape) A trace is printed in the console window. After several minutes you will have the printer output in the file LPT.txt.

   Its possible to run other carddecks by renaming it to CRD.cbn and putting it in this directory. This will work as long as no tape or drum is used.

Checking a change without looking at gtkwave:

The sort testbench ends with a check of the sorted memory cells and of the PROG STOP light, so the whole chain can be verified by one command from the Testbench folder:

 ./check.sh          (Windows: check.cmd)

It converts the schematics, compiles I704.v, runs the sort test and reports PASS or FAIL. The exit code is 0 only when everything passed, so it can be used in a script or on CI. Add --all to also run the card reader boot test and check that LPT.txt contains HELLO WORLD; that part takes some minutes. A simulation that does not finish is reported as a failure after a time limit (600 s for the sort test), because a damaged schematic can otherwise just run on.