Video slice changes - #979
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…_stage iris_set_stage() computes work_mode and sends it to firmware but never updates inst->fw_caps[STAGE].value, leaving the cached STAGE value stale. iris_vpu_enc_bin_size() and iris_vpu3x_vpu4x_calculate_frequency() read this cached value, so a stale default causes them to miscalculate buffer size and clock frequency for sessions actually running in a different stage than the cached one. Update inst->fw_caps[cap_id].value with the computed work_mode before sending it to firmware, keeping the cache consistent with what is actually configured. Link: https://lore.kernel.org/all/20260728-iris_multi_slice-v8-1-eb18f96f0ed8@oss.qualcomm.com/ Fixes: 3a19d7b ("media: iris: implement set properties to firmware during streamon") Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Sachin Kumar Garg <sachin.garg@oss.qualcomm.com>
iris_set_stage() currently always picks STAGE_2 for encoder sessions. CBR rate control requires stage 1 operation, so force STAGE_1 when BITRATE_MODE is set to CBR. The BITRATE_MODE fw_cap value is used instead of inst->hfi_rc_type since STAGE precedes BITRATE_MODE in enum platform_inst_fw_cap_type, so iris_set_properties() would still see the previous hfi_rc_type when iris_set_stage() runs during initial config Link: https://lore.kernel.org/all/20260728-iris_multi_slice-v8-2-eb18f96f0ed8@oss.qualcomm.com/ Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Sachin Kumar Garg <sachin.garg@oss.qualcomm.com>
Add multi-slice encoding support with MAX_MB and MAX_BYTES modes. Clients can enable slice mode using V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE control and configure slice size via V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB or V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES controls. Link: https://lore.kernel.org/all/20260728-iris_multi_slice-v8-3-eb18f96f0ed8@oss.qualcomm.com/ Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Sachin Kumar Garg <sachin.garg@oss.qualcomm.com>
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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Merge Check Failed: CR Not Eligible for Merge CR 4650099 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Hi All,
Above series adds support for multi-slice encoding in the Qualcomm Iris
driver.
Patch 1 is a prerequisite fix: iris_set_stage() computes a work_mode
but never caches it back into inst->fw_caps[STAGE].value, leaving
buffer-size and clock-frequency calculations based on a stale value.
Patch 2 is another prerequisite fix: iris_set_stage() currently always
selects STAGE_2 work mode for encoder sessions, but CBR rate control
requires STAGE_1. This is fixed by forcing STAGE_1 when BITRATE_MODE is
set to CBR.
Patch 3 adds the multi-slice support itself for Iris HFI Gen2 based
targets.
CRs-fixed: 4650099