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[CUDA] Add MoEPacked CPU/GPU hybrid offload and consolidate QMoE/GGUF offload optimizations - #33973

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tlwu/20261107/qwen38-rc5-gguf-offload
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Tianlei Wu (tianleiwu) wants to merge 5 commits into
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tlwu/20261107/qwen38-rc5-gguf-offload

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@tianleiwu Tianlei Wu (tianleiwu) commented Nov 8, 2026 •

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Summary

This draft PR consolidates and optimizes CPU/GPU hybrid expert offload for com.microsoft::MoEPacked (GGUF sub-byte block-packed experts) and com.microsoft::QMoE (RC5 mixed-precision INT4/INT3/INT2 experts) across 16 GB (RTX 5060 Ti), 24 GB (RTX 4090), 32 GB (RTX 5090), and H200 GPUs.

Stacked On

Key Changes

  1. End-to-End CPU/GPU Hybrid Offload for com.microsoft::MoEPacked (session_state.cc, moe_packed.h, moe_packed.cu, moe_packed.cc):
    • Places MoEPacked expert weight initializers (gate_weights, up_weights, down_weights) on CPU (zero-copy file mapping) and implements IMoeOffloadNode admission with QMoESessionController.
    • Implements CUDA-graph-capturable hybrid doorbell decode (MoEPackedOffloadClassifyAndBuildTilesKernel, MoEPackedDoorbellWaitKernel, MoEPackedOffloadFinalizeVec8Kernel, and LaunchQMoETailSubstitution integration) and 8,192-row double-buffered 32-expert wave-streaming prefill with D2D adaptive hot-expert promotion.
  2. Lock-Free qmoe::SpinPool & Register-Accumulator AVX2+FMA+F16C GGUF Cold-Expert Kernels (moe_packed.cc, cmake/onnxruntime_providers_cuda*.cmake):
    • Backs MoEPackedParallelPool with qmoe::SpinPoolRegistry (qmoe_spin_pool.h) and pins MoEPackedDoorbellService to CpuForWorker(0).
    • Implements pure register-accumulator 2-channel (GgufDualDot2ChAvx2Tpl<RT>) and 4-column (IQ4_NL/Q2_0) AVX2+FMA+F16C kernels covering IQ2_S, IQ2_XXS, IQ2_XS, IQ3_XXS, IQ4_XS, IQ4_NL, Q2_0, Q5_0, and mixed gate_type != up_type layers, cutting iq3_xxs CPU cold-expert latency 4.8x (245.5 us/exp -> 49.2 us/exp) and boosting iq3_xxs decode throughput 4.1x (16.2–20.8 tok/s -> 67.2–81.7 tok/s lossless, 179.96 tok/s with tail substitution) and iq1_s decode throughput up to 142.91 tok/s lossless (261.65 tok/s with tail substitution) on RTX 5090.
  3. QMoE INT2 Prefill & AVX-512 Cold-Expert Optimizations + 16 GB / 24 GB / 32 GB WDDM Reserve Calibration (qmoe_offload.cc, moe_gemv_tc.cuh, qmoe_shared_layout_int2_avx512.cc, qmoe_session_controller.h):
    • Dispatches MoeGemvTcInt2Kernel on sorted expert_map prefill waves (+24% to +30% faster 8K/32K prefill on 2b375, reaching 2,560 tok/s).
    • Extends Int2Group8Avx512 to RT = 1..4 with factored scale FMA.
    • Calibrates WDDM post-session reserves across 16 GB, 24 GB, and 32 GB GPUs for both QMoE and MoEPacked and auto-detects 8-byte vs. 4-byte STRP v1 popularity profiles.

Accuracy & Performance Impact of Tail Expert Substitution ( hreshold = 0.02, min_rank = 2) on 2b375 (RTX 5090 32 GB)

Evaluated on qwen_flash_next_int4_int8_rc5_contrib_dflash2_qmoe_2b375_x02_y14_z32_dp23_b64_unified (xhigh reasoning, greedy decoding):

  • MMLU-Pro (400 samples, max_new_tokens = 32,768):
    • Without TailSub ( hr = 0.0): 82.75% (331/400, strict 81.75%), median 162.09 tok/s, token-weighted 230.99 tok/s
    • With TailSub ( hr = 0.02, r = 2): 83.25% (333/400, strict 82.25%) (+0.50 pp, 12W / 10L, McNemar p = 0.8318), median 255.64 tok/s (1.58x faster), token-weighted 328.52 tok/s (1.42x faster)
  • LiveCodeBench v6 (175 problems, 256K = 262,144 limit):
    • Paired 161 / 175 problems on RTX 5090: 83.85% (135/161) With TailSub vs. 83.23% (134/161) Without TailSub (+0.62 pp, 13W / 12L, McNemar p = 1.0000), median 217.27 tok/s (1.54x faster), token-weighted 248.82 tok/s (1.65x faster)
    • Full 175 / 175 problems (at 256K): 77.14% (135/175, 43/43 = 100% Easy, 42/52 = 80.8% Medium, 50/80 = 62.5% Hard, conditional 88.24% when code is emitted) vs. 82.86% (145/175) lossless H200 reference.

…ffload optimizations

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
…zations

- Replace MoEPackedParallelPool with qmoe::SpinPoolRegistry and pin doorbell thread to CpuForWorker(0), eliminating epoch/remaining counter race and scheduler barrier stalls
- Add register-accumulator AVX2+FMA+F16C cold-expert kernels for IQ3_XXS, IQ4_XS, IQ2_S, IQ2_XXS, IQ2_XS, IQ4_NL, Q2_0, Q5_0, and mixed gate/up types with /arch:AVX2 on MSVC
- Extend Int2Group8Avx512 to RT=1..4 and factor block scales into single FMA
- Calibrate 16GB and 32GB WDDM post-session reserves for MoEPacked and QMoE, and filter PrefetchVirtualMemory by stream_skip

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Use checked workspace sizing for 8192-row offload prefills and allocate offload outputs before dispatch. Preserve shared-provider include ordering and enable the required AVX2, FMA, and F16C flags for Linux builds. Initialize pinned decode state correctly and preserve prefill staging type linkage under warnings-as-errors.

Extend offload parity coverage to empty input and prefills beyond 2048 rows.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
@tianleiwu
Tianlei Wu (tianleiwu) force-pushed the tlwu/20261107/qwen38-rc5-gguf-offload branch from 200420e to 0482c13 Compare November 9, 2026 19:55
@tianleiwu Tianlei Wu (tianleiwu) changed the title [CUDA] Add MoEPacked CPU/GPU hybrid offload and consolidate QMoE/GGUF offload optimizations (stacked on #33935, #33944, #33877, #33953) [CUDA] Add MoEPacked CPU/GPU hybrid offload and consolidate QMoE/GGUF offload optimizations Nov 9, 2026
Merge pinned main 3bde254 (23 commits ahead of the previous merge base 548473f, the #33953 merge).

Conflict resolution: js/react_native/e2e/test/OnnxruntimeModuleExample.test.js took main's version.
Main already selects the EPContext button on iOS via testID/by.id (e2a328f). The branch's
by.label selector matches two nested views on iOS ("Multiple elements found"), so the branch
no longer touches the React Native e2e test.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
@tianleiwu
Tianlei Wu (tianleiwu) marked this pull request as ready for review November 10, 2026 07:21
Copilot AI balanced review requested due to automatic review settings November 10, 2026 07:21

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