Update from task cdf7a3e5-93eb-47e5-8875-a11899703d3f

.github/workflows/ci.yml

@@ -0,0 +1,55 @@
+name: CI
+
+on:
+  push:
+    branches: [ main, develop ]
+  pull_request:
+    branches: [ main ]
+
+jobs:
+  lint-and-compile:
+    runs-on: ubuntu-latest
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Install Verilator
+      run: |
+        sudo apt-get update
+        sudo apt-get install -y verilator
+
+    - name: Compile RTL sources
+      run: |
+        cd sim
+        make TOP_MODULE=tb_matrix_multiply_2x2
+
+    - name: Compile AXI testbench
+      run: |
+        cd sim
+        make clean
+        make TOP_MODULE=tb_axi4_lite_core_ctrl
+
+  sanity-check:
+    runs-on: ubuntu-latest
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Check file structure
+      run: |
+        test -d rtl/math_core || exit 1
+        test -d rtl/memory || exit 1
+        test -d rtl/hdc || exit 1
+        test -d rtl/bus || exit 1
+        test -d rtl/top || exit 1
+        test -d tb || exit 1
+        test -d sim || exit 1
+        echo "✓ Directory structure is correct"
+
+    - name: Verify critical files exist
+      run: |
+        test -f rtl/math_core/softmax_core.sv || exit 1
+        test -f rtl/math_core/systolic_array_param.sv || exit 1
+        test -f rtl/hdc/hdc_distance_core_v3.sv || exit 1
+        test -f rtl/bus/axi4_lite_core_ctrl.sv || exit 1
+        echo "✓ All critical RTL files present"

.gitignore

@@ -1,68 +1,46 @@
 ```
-# Compiled and binary files
+# Compiled and build artifacts
 *.pyc
-*.class
+__pycache__/
 *.o
-*.exe
-*.dll
-*.so
-*.a
 *.obj
 *.out
+build/
+dist/
+target/
 
 # Dependencies
 node_modules/
 venv/
 .venv/
-__pycache__/
-dist/
-build/
-target/
-.gradle/
-.mypy_cache/
-.pytest_cache/
+.env
+.env.local
+.env.*
 
-# Editor/IDE files
+# Logs and temp files
+*.log
+*.tmp
+*.swp
+
+# Editors
 .vscode/
 .idea/
-*.swp
-*.swo
-*.tmp
 
-# System/Environment files
+# OS specific
 .DS_Store
 Thumbs.db
-.env
-.env.local
-*.env.*
 
-# Logs and coverage
-*.log
+# Coverage
 coverage/
 htmlcov/
 .coverage
 
-# Compressed files
-*.zip
-*.gz
-*.tar
-*.tgz
-*.bz2
-*.xz
-*.7z
-*.rar
-*.zst
-*.lz4
-*.lzh
-*.cab
-*.arj
-*.rpm
-*.deb
-*.Z
-*.lz
-*.lzo
-*.tar.gz
-*.tar.bz2
-*.tar.xz
-*.tar.zst
+# Gradle
+.gradle/
+
+# MyPy
+.mypy_cache/
+
+# Pytest
+.pytest_cache/
 ```

doc/ARCHITECTURE.md

@@ -0,0 +1,71 @@
+# Open Cognitive Core Architecture
+
+## Overview
+
+The Open Cognitive Core Project (OCCP) is a hardware accelerator for Hyperdimensional Computing (HDC) and lightweight neural network operations, designed for FPGA implementation.
+
+## System Architecture
+
+```
++------------------------------------------------------------------+
+|                     AXI4-Lite Control Bus                         |
+|  (RISC-V / CPU Control Interface)                                |
++------------------------------------------------------------------+
+                              |
+        +---------------------+---------------------+
+        |                                           |
+        v                                           v
++-------------------+                   +-------------------+
+|   HDC Subsystem   |                   |   ML Subsystem    |
+|                   |                   |                   |
+|  +-------------+  |                   |  +-------------+  |
+|  | N-gram      |  |                   |  | SRAM Skew   |  |
+|  | Encoder     |--+                   |  | Buffer      |--+
+|  +-------------+  |                   |  +-------------+  |
+|        |          |                   |        |          |
+|        v          |                   |        v          |
+|  +-------------+  |                   |  +-------------+  |
+|  | Distance    |  |                   |  | Systolic    |  |
+|  | Core        |  |                   |  | Array       |  |
+|  +-------------+  |                   |  +-------------+  |
+|                   |                   |        |          |
++-------------------+                   |        v          |
+                                        |  +-------------+  |
+                                        |  | ReLU        |  |
+                                        |  +-------------+  |
+                                        |        |          |
+                                        |        v          |
+                                        |  +-------------+  |
+                                        |  | Softmax     |  |
+                                        |  +-------------+  |
+                                        +-------------------+
+```
+
+## Module Descriptions
+
+### HDC Subsystem
+
+| Module | Function | Status |
+|--------|----------|--------|
+| `hdc_ngram_encoder_v3` | Encodes token sequences into hypervectors | Complete |
+| `hdc_distance_core_v3` | Computes Hamming distance between HVs | Complete |
+
+### ML Subsystem
+
+| Module | Function | Status |
+|--------|----------|--------|
+| `sram_skew_buffer` | Cycle delays for systolic timing | Complete |
+| `systolic_array_param` | Matrix multiplication engine | Complete |
+| `relu_activation` | ReLU activation function | Complete |
+| `softmax_core` | Safe softmax with LUT | Fixed v1.0.1 |
+
+### Control & Interface
+
+| Module | Function | Status |
+|--------|----------|--------|
+| `axi4_lite_core_ctrl` | AXI4-Lite slave interface | Complete |
+| `open_cognitive_top` | Top-level integration | Complete |
+
+## License
+
+CERN-OHL-W v2