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leandrotozzi/README.md

Hi, I'm Leandro 👋

Digital design & verification engineer working on mixed-signal ICs. I like SystemVerilog, UVM, and making open-source EDA tools do real work.

Projects

  • verifythis — a free UVM course that runs end to end on Verilator, no EDA licences. English & Spanish.
  • sv-skill — Claude Code skill + svstyle checker for clean, synthesizable SystemVerilog RTL.
  • python-dpic — Python connected to UVM environments via DPI-C.

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  1. python-dpic python-dpic Public

    Hands-on SystemVerilog DPI-C tutorial on Verilator, ending with embedded Python as a bit-exact golden model. 8 steps, labs checked in CI.

    HTML 1

  2. aws-fpga aws-fpga Public archive

    Forked from aws/aws-fpga

    Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

    VHDL

  3. PDK_ONC5 PDK_ONC5 Public

    Forked from UNSAMDCI/PDK_ONC5

    Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library

    HTML

  4. riffa riffa Public archive

    Forked from KastnerRG/riffa

    The RIFFA development repository

    Verilog

  5. sv-skill sv-skill Public

    Claude Code skill and svstyle checker for clean, synthesizable SystemVerilog RTL in a lowRISC-derived style

    SystemVerilog

  6. verifythis verifythis Public

    A free UVM course that runs end to end on Verilator — no EDA licences. 8 units over 7 days (plus an optional day 8), 444 slides, 38 runnable examples with functional coverage, 19 exercises and an A…

    HTML