Electrical engineering student at Valparaiso University (Christ Honors College), transferred from Purdue. I work in digital logic, circuit analysis, FPGA/RTL design, and undergraduate research in robotic cybersecurity and volumetric additive manufacturing. Seeking a Summer 2027 electrical or hardware engineering internship.
🌐 austinguerrero.dev · 💼 LinkedIn · ✉️ austin.guerrero@valpo.edu
- Heartbeat Theory for Robotic Cybersecurity: e-puck and Kilobot swarm robots
- Volumetric Additive Manufacturing: ultrasonic transducers in the VAM system
- Wearable EEG Concussion Scanner: IEEE SMC, Purdue
- FPGA Stopwatch System: SystemVerilog, Purdue SoCET
- Design Project 1: Universal Gates and NOR-Only Half Adder: A complete half adder built from only two-input NOR gates
- Lab 2: Half-Adder Implementation: 25 ns measured input-to-SUM propagation delay
- Design Project 2: Logic Minimization: Excess-3 to 2-of-5 Code Converter: 19 gates on 5 ICs (minimum-IC design) vs. 22 gates on 7 ICs (minimum-gate design)
- Lab 3: Excess-3 to 2-of-5 Code Converter in Hardware: 23.2 ns worst-case propagation delay
- Design Project 3: 4-Bit Ripple Adder/Subtractor: Six gates per cell; four hierarchical cells form a 4-bit 2's complement adder/subtractor
- Lab 4: Wheatstone Bridge: Measuring Resistance: Every bridge estimate within 2.8% of the DMM; five of nine within 1%
- Lab 5: MATLAB and Systems of Equations: Nodal analysis solved with rref: i5 = 1.352 A
- Lab 6: Mesh and Nodal Analysis of a Two-Source DC Network: Hand analysis and CircuitLab agreed within 0.05%
- Lab 7: Thevenin Equivalents and Maximum Power Transfer: 73.60 mW to the matched load vs. 74.67 mW theoretical maximum
- 12-Band Audio Equalizer: ECE 20007, Purdue
OrCAD Capture · PSpice · LTspice · CircuitLab · MATLAB · SystemVerilog · Python · C · KiCAD · SolidWorks · Excel/VBA