Hello,
I have seen your question on SO and because I also currently develop an own small kernel (but not in Rust, but currently closed) I have thought to give you some suggestions and help to narrow down your issue and also other recommendations.
Issue:
For the real issue because it doesn't run on real hardware I need more time to investigation. It's currently only a guess but because you setup and enable the MMU first before you switch to EL1 and the page tables are at a address higher than 0xFFFFFF8000080000, the MMU can't access it when you setup TBBR1_EL1 and TBBR0_EL1. Keep in mind the page tables must stay at a physical address below 0x0001000000000000 because bits 63:48 in TBBR1_EL1/TBBR0_EL1 defines the ASID.
You can see that here:
TTBR1_EL1, Translation Table Base Register 1 (EL1)
I will add some additional information, when I know that is the real issue.
MPCore:
The Raspberry Pi 3b+ includes a Cortex-A53 quad core processor. I haven't seen yet in your code how you handle this behavior. To avoid race conditions and other side effects I would suggest to let only one core keep running yet. Later you can add also SMP support if you like.
Example snippet from to check if we run on core0:
6000:
mrs x0, MPIDR_EL1
/**
* Test if system is a uniprocessor system
*/
mov x1, xzr
orr x1, x1, #(1 << 30) /* U-bit in MPIDR_EL1 register */
and x2, x0, x1 /* Mask U-bit */
cmp x0, x2 /* Test if a uniprocessor system */
beq 5000f /* Branch to EL3 setup if a uniprocessor system */
/**
* Test if we run on core 0
*/
and x0, x0, #0xFF /* Mask Affinity 0 (Aff0) field */
cmp x0, #0 /* Test if core 0 */
beq 5000f /* Branch to EL3 setup, if true */
/**
* Wait forever if we are not core0 currently.
*/
6001:
wfe
b 6001b
5000:
EL3:
It's only a guess from me, but I think the Cortex-A53 starts at Exception level 3 (EL3) also on the Raspberry Pi 3b+. If yes (not tested on real hardware yet), than you should also add the required setup steps in your entry assembly code.
I could also provide here some snippets if you like.
Hello,
I have seen your question on SO and because I also currently develop an own small kernel (but not in Rust, but currently closed) I have thought to give you some suggestions and help to narrow down your issue and also other recommendations.
Issue:
For the real issue because it doesn't run on real hardware I need more time to investigation. It's currently only a guess but because you setup and enable the MMU first before you switch to EL1 and the page tables are at a address higher than
0xFFFFFF8000080000, the MMU can't access it when you setupTBBR1_EL1andTBBR0_EL1. Keep in mind the page tables must stay at a physical address below0x0001000000000000because bits 63:48 inTBBR1_EL1/TBBR0_EL1defines the ASID.You can see that here:
TTBR1_EL1, Translation Table Base Register 1 (EL1)
I will add some additional information, when I know that is the real issue.
MPCore:
The Raspberry Pi 3b+ includes a Cortex-A53 quad core processor. I haven't seen yet in your code how you handle this behavior. To avoid race conditions and other side effects I would suggest to let only one core keep running yet. Later you can add also SMP support if you like.
Example snippet from to check if we run on core0:
EL3:
It's only a guess from me, but I think the Cortex-A53 starts at Exception level 3 (EL3) also on the Raspberry Pi 3b+. If yes (not tested on real hardware yet), than you should also add the required setup steps in your entry assembly code.
I could also provide here some snippets if you like.