ppl: block regions overlapping pdn wires and obstructions - #11099
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eder-matheus wants to merge 18 commits into
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ppl: block regions overlapping pdn wires and obstructions#11099eder-matheus wants to merge 18 commits into
eder-matheus wants to merge 18 commits into
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Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
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Code Review
This pull request enhances the I/O Placer to respect routing obstructions and Power Delivery Network (PDN) shapes near the die boundary, ensuring proper spacing for placed pins. It introduces caching for pin sizes and layer spacing, updates Hungarian matching to avoid blocked mirrored slots, and refactors getters in Core to return const references. The review feedback focuses on improving code robustness and performance in IOPlacer.cpp, specifically by optimizing map lookups to avoid double lookups or std::out_of_range exceptions, adding null checks for tech_layer and top_grid_, and ensuring non-routing layers are handled correctly.
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
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Summary
place_pinsandplace_pinignored boundary power grid geometry, so signal IOpins were placed on top of or abutting
-extend_to_boundarystraps and thepower/ground BPins
pdngencreates there, causing shorts and spacing violationsfound only at detailed route.
Blocking shapes are now padded by the pin footprint plus the required spacing,
applied uniformly to special net wires, via landing pads, routing obstructions
and fixed pins, including shapes within pin reach of the edge. Also fixed while
here: mirrored pins landing on blocked slots, polygon dies ignoring blocked
regions,
place_pinunaware of this geometry, width dependent(PARALLELRUNLENGTH) spacing for wide straps, and MINSPACING/EFFECTIVEWIDTH
attributes being discarded.
getBlockedRegionsFromDbObstructions()was deadcode and is now wired in.
Type of Change
Impact
Slots too close to boundary PDN geometry become unavailable, so IO pin positions
change in designs with boundary PDN (slightly different HPWL). Designs without
it are unaffected — no golden file changes in pre existing tests. A constrained
region fully covered by the power grid now fails with PPL-76/PPL-82 instead of
producing violations.
Verification
./etc/Build.sh).162/162 ppl tests pass, including 13 new ones. Also verified the
place_pinsconsumers in gpl, odb, rsz and mpl.
Related Issues
Fixes https://github.com/The-OpenROAD-Project-private/OpenROAD/issues/3655