A quadrature encoder interface with four-times decoding and illegal-transition detection.
Part of the Tape-Out IP library: Bluespec IP over the bus-neutral contracts in
hwcore, assembled by xirang. Maturity runs
planned -> simulated -> fpga-proven -> asic-ready -> silicon-proven.
Planned. The skeleton implements a scratch register mirrored to a read-only register while enabled, so that generation, type checking and the register consistency test all have something real to run against. Replace it.
| Parameter | Range | Meaning |
|---|---|---|
dataWidth |
1 to 32 | width of data and mirror |
invert |
bool | mirror the complement |
| Offset | Register | Contents |
|---|---|---|
| 0x00 | ctrl |
bit 0 enables the mirror |
| 0x04 | data |
value written by software |
| 0x08 | mirror |
data while enabled, zero otherwise |
任选其一：
SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
除非另行说明，你提交的贡献按上述三者同时授权，不附加其他条件。