fix(fpga_diff): constrain XDMA pre-PERST CDC

[klin02]

The XDMA DCP imports the pre-PERST BUFG_GT clock as an independent primary clock, so the existing asynchronous clock groups do not cover its crossing to pcie_ep_refclk. Add an explicit asynchronous clock group in vivado_pre_opt.tcl after clock inference.

Validation:

• Tcl structural parse passed.
• KMHV2 F2 Vivado report_cdc changed the crossing exception from None to Asynch Clock Groups.
• P4 UVHS timing worker completed with 0 fatal and 0 error.