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[https://nvbugs/6902353][chore] Waive test_transfer_lifecycle_gpu[destination_fatal] - #20457
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…tination_fatal] The worker-startup timeout tracked by nvbugs/6902353 hits whichever case of test_transfer_lifecycle_gpu runs first on a node. With the other six cases waived, destination_fatal runs first and times out on every run. Signed-off-by: Yao Yao <lowsfer@users.noreply.github.com>
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/bot run --disable-fail-fast |
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/bot run --disable-fail-fast |
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Automatically added "ci: full pre-merge approved" because this PR has satisfied the required GitHub review approvals. Unresolved review conversations and other required checks remain independent merge requirements. |
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/bot skip --comment "waive only" |
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Dev Engineer Review
destination_fatalunder NVBUG 6902353. It does not change test code or runtime behavior.QA Engineer Review
tests/integration/test_lists/waives.txt. Added aSKIPentry fortest_transfer_lifecycle_gpu[destination_fatal].unittest/disaggregated/test_transfer_lifecycle_gpu.pyintest-db/l0_dgx_b200.yml. The waiver list now covers all seven test IDs reported for this module.Per-File QA Perspective
tests/integration/test_lists/waives.txt: Adds a waiver for thedestination_fataltest ID. The test database still lists the test module, while the waiver list covers its seven reported cases.Description
Waive
unittest/disaggregated/test_transfer_lifecycle_gpu.py::test_transfer_lifecycle_gpu[destination_fatal]under the existing NVBUG 6902353, alongside the six sibling cases waived in #20235.Why: the test waits 120 s for four native MPI ranks to come up. On a fresh CI node, whichever case runs first in the module pays a one-time startup cost and exceeds that deadline (
AssertionError: Timed out: four native MPI ranks). The later cases start warm.baselineran first and failed at 124.2 s; every other case, includingdestination_fatal(159.9 s), passed.baseline,cancel_before_publication,cancel_late_aux,cancel_late_kv,source_fatalandtimeout_late_aux, which leftdestination_fatalas the first and only case. It has failed in every run since: 16 of 16 x86-64 Multi-GPU runs from 2026-10-13 20:59Z through 2026-10-16, across 14 PRs (e.g. [None][perf] Do not block the executor on KV bounce recv-region backp… #19940, [None][feat] Stream native KV events and expose routing load #19440, [trtllm-agent][https://nvbugs/6812350][fix] Raise remote MPI worker exceptions from submit_sync #19561, [None][feat] Publish serving configuration schemas #19906, [None][fix] Enable VMM CUDA IPC in Kubernetes GPU CI #20042, [None][chore] Remove ArrayView and usestd::spaninstead #20205, [None][test] Migrate ordinary disaggregated coverage to KV cache manager V2 #20050, [None][fix] Merge back #19593 from release/1.3: Make MoE communication timeouts follow the warmup phase #20246, [None][feat] Add the PrimTS native sparse MLA FMHA for DeepSeek-V4 generation #20209, [None][perf] One-model speculative decoding: host work between steps, worker-produced target logits, KDA drafts' records #19989, [TRTLLM-16992][perf] Use paged attention for MiniMax-M3 dense layers #20159, [None][perf] primsTS dense bf16, qk-bf16/pv-fp8, fp8 fmha context bringup #20006, [None][perf] Fill the KVCM2 host tier progressively #19650), with no passes. Before the [https://nvbugs/6902353][chore] waive test_transfer_lifecycle_gpu #20235 waive it passed 6 of 6 times.This currently fails
DGX_B200-4_GPUs-PyTorch-3for every PR whose pipeline runs the x86-64 Multi-GPU leg. Single-GPU-only PRs never run it.Note on #20439 (unwaiving the six cases): with all seven cases enabled, the first case (
baseline) is expected to hit the same cold-start timeout again, as it did before #20235. The underlying fix is to give the first launch a longer startup deadline or warm the workers up once per module, which belongs to NVBUG 6902353.Test Coverage
Waive-only change; no code changes.
DGX_B200-4_GPUs-PyTorch-3should no longer run anytest_transfer_lifecycle_gpucase.PR Checklist
Please review the following before submitting your PR:
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PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
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Documentation updated as needed
Update tava architecture diagram if there is a significant design change in PR.
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