riscv: implement fcvtmod.w.d with modulo-2^32 semantics

[carlosqwqqwq]

riscv: implement fcvtmod.w.d with modulo-2^32 semantics

Commit message

riscv: implement fcvtmod.w.d with modulo-2^32 semantics

fcvtmod.w.d (Zfa) converts its double operand with round-towards-zero
and returns the low 32 bits of the rounded two's-complement result
(modulo 2^32, no saturation); NaN and infinity convert to 0.
The previous handler reused the saturating fpu_fcvt_f64_to_i32,
which yields 0x7fffffff/0x80000000 for out-of-range inputs and
saturates NaN/infinity.

Add fpu_fcvtmod_f64_to_i32 implementing the modulo semantics with
NV on NaN/inf/overflow and NX on inexact rounding, and use it from the
fcvtmod.w.d case. The separate architectural writeback control-flow fix is
tracked by PR #303.

Description

fpu_lib.h: new fpu_fcvtmod_f64_to_i32 performs RTZ rounding on the raw double bits, extracts the low 32 bits of the rounded value, and applies the sign; NV is raised for NaN/infinity/out-of-range, NX for inexact truncation. The in-range path uses direct bit-level extraction for the common case (|x| < 2^31).

riscv_fpu.c: case 0x08 calls the new routine; reserved rounding-mode
encodings retain the existing illegal path. The separate fall-through defect
is handled by PR #303, and this semantic patch remains independently
applicable to the same staging baseline.

Validation

• The 28-case boundary matrix matches QEMU -cpu max for the modulo result and
  fflags produced by this conversion path; instruction retirement remains the
  separate scope of PR riscv: return after valid fcvtmod.w.d #303.
• The saturating variant mismatches on 18/27 distinct cases, confirming the
  conversion semantics are independent of the control-flow defect in riscv: return after valid fcvtmod.w.d #303.

Fixes #297