[AdaWorldAPI]

Step 1 of the micro/macro sequence in synergy map R7.6: a packed 128-bit microtile, checked against an exact oracle. This is a lab fixture. It adds no public type, changes no backend and has no production caller. Steps 2–4 (binding to a KPEA method, reusing Thought-0 work across thought deltas, interlacing) are not started.

What it is

The fixture is examples/microtile/ (four realizations plus a cost gate) and tests/microtile.rs (exactness). One 128-bit tile holds one of two layouts:

• 5×U24/I24, plus 8 metadata bits;
• 14×U9/I9, plus 2 spare bits.

Operations:

• wrapping add and sub, with each carry and borrow kept inside its own field;
• per-field carry-out, borrow-out and signed overflow;
• an intra-tile stencil, f[j-1] + 2f[j] + f[j+1];
• an exact fold giving each field's unsigned and signed sum across many tiles.

Every result keeps the left operand's metadata.

Realizations

All four are checked against one unpacked per-field oracle:

1. u128: the whole tile in one 128-bit integer.
2. SoA U64x8: 8 tiles per operation, each tile split into a low and a high 64-bit word. The fields that cross bit 64 get an explicit carry or borrow out of bit 63, computed with lane-wise logic only.
3. Widened U32x16: one field per u32 lane. The fold flushes the lanes to u64 before they can overflow.
4. Bit planes: added with simd::full_add_mask, folded by popcount.

Tests

• 9 tests, green on AVX-512, AVX2, AVX (qemu SandyBridge), x86-64-v2 (qemu Nehalem), NEON (qemu aarch64) and nightly core::simd.
• Disable runs D1–D13 each turn the tests red, except D6: that one removed a redundant mask on the stencil's left shift, so I deleted the mask itself.
• Clippy (-D warnings, v3 and v4) and fmt are clean, and the FACET STRIDE guard passes.

Cost gate

x86 only; ns per tile, as the range across three runs. Full table in .claude/knowledge/microtile-probe.md. No realization wins every case:

• U24x5: widened is fastest for both add (≈0.7 at 4K tiles) and fold (≈0.3).
• U9x14:
  • packed SoA is fastest for add while the data fits in L2 (1.1–1.7, against ≈1.9 widened);
  • bit planes are fastest for the fold (0.6–0.8);
  • widened costs 3.5× the bytes and is about 3× slower at 1 MB.
• The single u128 never wins (about 2 ns/tile): rustc does not vectorize it, and the packed speed comes from the SoA split.

Found along the way

On NEON and wasm, U32x16 lacks &, |, -, !, +=, from_slice and copy_to_slice. The fixture works around this; the gap is recorded in the report, not fixed here.

No automatic merge.

---

Generated by Claude Code

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[chatgpt-codex-connector]

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Review	Status	Commit	Review trigger
📝 Code Review	✅ Completed 2026-10-30T13:40:25.220964Z	97d8cdd	Draft marked ready

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Reviewed commit: 97d8cdd5d0

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[chatgpt-codex-connector]

Materialize and consume the bit-plane addition results

In the release cost gate, every bit-plane block writes its sum into the same op scratch buffer, but that buffer is never read; only the carry masks reach black_box. Because planes_add is inlined, the optimizer can eliminate the sum calculations and stores, leaving a carry-only benchmark. Even without that optimization, this path avoids writing a complete result dataset, unlike the other three addition paths. This makes the reported addition timings and bandwidth conclusions incomparable. Store each block's sum in a full output buffer and pass that output through black_box inside the timed closure.

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