amx_matmul: make matmul_f32 exact; AMX f32 paths become named opt-ins - #303
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`matmul_f32` on an AMX host downcast both operands to BF16 once and ran TDPBF16PS. The one-rounding-then-f32-accumulate discipline was correct and intact; what it cannot do is recover the 16 significand bits that single rounding discards. Measured: ~1e-3 relative error (bf16 mantissa, eps 7.8e-3, f32 accumulate), uniform across aligned and ragged shapes, while the API returned Ok(()) under an f32 name. Routing burn's burn-ndarray through it failed 50 linalg tests (25 qr, 13 lu, 7 svd, 3 det, 1 attention) that pass at 1826/1826 on the exact path. The existing test could not see this: its inputs `(i+j)*0.5` and `(i*3+j)*0.25` are all exactly BF16-representable, so the downcast was lossless by construction, and its AMX tolerance was 1%. It now uses irrational inputs at 1e-5. Two candidate fixes were built and benchmarked against each other and against the CPU f32 paths (`gemm_paths_bench`, Xeon w/ AMX + AVX-512, square f32, release): size native gemm_f32 F32x16 sgemm_blocked AMX 3-pass split AMX 1-pass 256 0.42ms 2.9e-7 0.37ms 2.9e-7 2.78ms 1.4e-6 0.77ms 3.7e-4 512 3.51ms 1.2e-6 3.22ms 1.2e-6 20.9ms 1.4e-6 6.37ms 2.2e-4 1024 28.8ms 1.4e-6 27.3ms 1.4e-6 159ms 1.5e-6 45.9ms 1.6e-4 AMX loses on both axes at every size. The three-pass BF16 hi/lo split does reach f32 grade (~400x better than one pass) but is ~6x slower than the exact CPU kernel it was meant to replace, and even the lossy single pass is slower than plain f32. Packing, conversion and passes cost more than the tile unit saves for f32. So: - `matmul_f32` now delegates to `backend::native::gemm_f32` and is exact, on every host. It never touches AMX. - `matmul_f32_amx_split` (the three-pass split) and `matmul_f32_bf16_fast` (the old single pass) are kept as explicitly named opt-ins with the table above in their docs, so the measurement is reproducible and a future host or a real f32 tile op can be re-measured against them. Neither is recommended. - `three_pass_split_beats_one_bf16_pass` pins all three two-sided: the default at <=1e-5, the split at <=1e-5 and >=50x better than one pass, and the one pass at >1e-4 — the last so that if AMX ever gains a real f32 op the cost is re-justified rather than assumed. - `gemm_paths_bench` (`#[ignore]`, `--release`) is the bench above. The one-rounding technique was the right half of the answer; this change adds the other half, then measures that neither half beats not using AMX for f32 at all. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01EfrUJH3UNnv5NpDH4jDGHq
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📝 WalkthroughWalkthroughChangesThe f32 matmul API now provides separate exact CPU, single-pass BF16 AMX, and three-pass BF16-split AMX paths. Tests validate accuracy differences, and an ignored benchmark compares performance and error across workloads. Matmul path separation
Estimated code review effort: 4 (Complex) | ~45 minutes Merge Risk: 🟡 Moderate · up to The new AMX split opt-in can return NaN for valid large or infinite f32 inputs, producing incorrect matrix results. Add a safe fallback or enforce and document supported input bounds before merge. Suggested reviewers: Poem
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…for #303 Source-first plan for the operator ask "consolidate gemm, ternlogq chaining and cached mask reuse". Inventory: 54 gemm/matmul entry points across 12 files, 4 unified. Three seams with one rule each; six frozen decisions; a measure-first Wave 0 of six probes; nothing in W1+ built. Cached-mask reuse is consumed from lance-graph-java's mask-risc-lowering-v1 (v4.2), not re-planned — this plan's one ask of it is a carving kind for a compacted GEMM row-index list (D-GTM-6). Blackboard records the #303 finding, the bench that decided it, and the loose ends (burn's amx-f32 gate, blas_level3's empty grep, the bf16_tile_gemm_16x16 name duplicate). Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01EfrUJH3UNnv5NpDH4jDGHq
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In `@src/hpc/amx_matmul.rs`:
- Around line 733-735: Update the BF16 splitting path around
BF16::from_f32_rounded so non-finite inputs and finite values whose rounded head
is non-finite bypass the three-pass AMX computation and use
backend::native::gemm_f32 instead. Preserve the existing AMX path for safely
representable inputs, and add coverage for infinity and BF16-rounding overflow
cases.
- Around line 748-750: Add runnable /// documentation examples for the public
functions matmul_f32_bf16_fast, matmul_f32, and matmul_f32_amx_split in
src/hpc/amx_matmul.rs at lines 748-750, 781-783, and 810-812 respectively; each
example should construct suitable inputs, call its function, and handle the
Result, with the first documenting AMX/fallback behavior and the third
documenting its accuracy/performance tradeoff.
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… doc examples CodeRabbit (#303) found a real hole in both AMX opt-ins: `f32::INFINITY` splits as `h = inf`, `x - h = NaN`, and the three-pass cross term then multiplies `inf` by zero. `f32::MAX` is the finite version — its RNE BF16 head rounds to `inf` (bit-trick `from_f32_rounded`: `0x7F7F` + round + sticky = `0x7F80`). Either way a NaN lands in the product under an `Ok(())`. `bf16_safe` checks every value is finite AND its BF16 head is finite; `matmul_f32_amx_split` and `matmul_f32_bf16_fast` take the tile path only when both operands pass, else the exact CPU reference they already carried. `matmul_f32` is untouched — it never went near BF16. Two-sided test: the premise (`f32::MAX` → BF16 inf) is asserted before anything else, then `inf` and `f32::MAX` poison one cell of an otherwise irrational fixture and both opt-ins must return no NaN and match the reference; ordinary large values (`-3.0e38`) and subnormals must NOT trip the guard. Clippy caught the first fixture: `3.5e38` is above `f32::MAX` — the "representable" example wasn't. Runnable `# Example` blocks on all three public fns (the repo rule); 3/3 doctests pass. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01EfrUJH3UNnv5NpDH4jDGHq
…1 gains a shape guard Operator objection to the bench: 256/512/1024 are undersized. Extended to 2048³, 4096³ (1.6 s per GEMM, well past cache-resident), 1024×4096×1024, 256×8192×256 and 64×2048×8192. AMX does not converge with size: 1-pass stays 1.75x slower than the F32x16 kernel at 4096³, 3-pass 5x. The conclusion about AMX for f32 stands at every size measured. Size did expose one real thing: on the two skinny rectangles matrixmultiply beats sgemm_blocked by 10-19% — its MC=72/NC=256 blocking is tuned for square-ish operands. D-GTM-F1 now carries a shape guard whose threshold D-GTM-0c measures, rather than a blanket default. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01EfrUJH3UNnv5NpDH4jDGHq
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The defect
matmul_f32on an AMX host downcast both operands to BF16 once and ranTDPBF16PS. The one-rounding-then-f32-accumulate discipline was correct and intact — but it cannot recover the 16 significand bits that the single rounding discards. Measured ~1e-3 relative error (bf16 mantissa, eps 7.8e-3, f32 accumulate), uniform across aligned and ragged shapes, while the API returnedOk(())under an f32 name.Routing burn's
burn-ndarraythrough it fails 50 linalg tests (25 qr, 13 lu, 7 svd, 3 det, 1 attention) that pass at 1826/1826 on the exact path — that is how it was found (AdaWorldAPI/burn#9).The existing test could not see it. Its inputs
(i+j)*0.5and(i*3+j)*0.25are all exactly BF16-representable, so the downcast was lossless by construction — and its AMX tolerance was 1%. It could neither detect nor fail on the loss. Now irrational inputs at 1e-5.What was measured before choosing a fix
Two candidates were built and benchmarked against each other and against the CPU f32 paths (
gemm_paths_bench, Xeon w/ AMX + AVX-512, square f32,--release):native::gemm_f32sgemm_blockedAMX loses on both axes at every size. The three-pass BF16 hi/lo split does reach f32 grade (~400× better than one pass) — but it is ~6× slower than the exact CPU kernel it was meant to replace, and even the lossy single pass is slower than plain f32. Packing, conversion, and passes cost more than the tile unit saves for f32. The zero-loss F32x16 backend already exists and is the fastest thing in the table.
The change (commit 1,
abd890b1)matmul_f32now delegates tobackend::native::gemm_f32and is exact on every host. It never touches AMX.matmul_f32_amx_split(three-pass split) andmatmul_f32_bf16_fast(the old single pass) are kept as explicitly named opt-ins, with the table above in their docs — so the measurement is reproducible and a future host, or a real f32 tile op, can be re-measured against them. Neither is recommended; neither is reachable by accident.three_pass_split_beats_one_bf16_passpins all three two-sided: the default at ≤1e-5; the split at ≤1e-5 and ≥50× better than one pass; the one pass at >1e-4 — the last so that if AMX ever gains a real f32 op, the cost gets re-justified instead of assumed.gemm_paths_bench(#[ignore],--release) is the bench above, in-crate so it can reach thepub(crate)F32x16 kernel.matmul_bf16_to_f32andmatmul_i8_to_i32are untouched — BF16 and INT8 are what the tile unit is for.The plan (commit 2,
7b21f6cf, docs only).claude/plans/gemm-ternlog-mask-consolidation-v1.md— DRAFT v1, source-first, for the operator ask "consolidate gemm, ternlogq chaining and cached mask reuse". Inventory: 54gemm|matmulentry points across 12 files, 4 unified. One facade per dtype (D-GTM-F3); F32x16sgemm_blockedas the exact default (D-GTM-F1); ternlog chaining at T1 feeding a compacted-index GEMM prefilter (D-GTM-F4); six measure-first W0 probes; nothing in W1+ built. Cached-mask reuse is consumed from lance-graph-java'smask-risc-lowering-v1(v4.2), not re-planned — the one ask of that plan is a carving kind for a GEMM row-index list (D-GTM-6). Blackboard entry prepended per the repo rule.Verification
hpc::amx_matmul12/12 (1 ignored bench);cargo clippy --lib --tests -- -D warningsclean;cargo fmt --checkclean.Follow-ups (not this PR)
gemm_f32throughsgemm_blockedonavx512fhosts (~12% faster, equally exact) — oneunsafecall with a SAFETY comment; wants D-GTM-0c's non-square/tail measurement first.amx-f32feature (Re-wire burn-ndarray onto the AdaWorldAPI/ndarray SIMD polyfill burn#9) becomes pointless once this lands — delete it rather than keep it off.🤖 Generated with Claude Code
https://claude.ai/code/session_01EfrUJH3UNnv5NpDH4jDGHq