From ae8d44e21207c35fd8c7ae21fe1b2425c2b50697 Mon Sep 17 00:00:00 2001 From: Navya Malempati Date: Fri, 22 May 2026 16:40:13 +0530 Subject: [PATCH] UPSTREAM: arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states Firmware supports both CPU power collapse (little/big_cpu_sleep_0) and CPU PLL/rail power collapse (little/big_cpu_sleep_1) idle states. However, CPU power collapse modes are often not utilized in favor of performance, so remove the CPU power collapse modes for monaco, aligning with SM8350/SM8450/SM8550/SM8650. Rename little/big_cpu_sleep_1 as little/big_cpu_sleep_0 since it is now the only CPU idle state in use. Signed-off-by: Navya Malempati Reviewed-by: Maulik Shah Link: https://lore.kernel.org/r/20260522-ml_cpuidle-v1-1-fd311cf33fb4@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 36 +++++++--------------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d944da523804..a5c9d579c805 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -349,16 +349,6 @@ entry-method = "psci"; little_cpu_sleep_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "silver-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <449>; - exit-latency-us = <801>; - min-residency-us = <1574>; - local-timer-stop; - }; - - little_cpu_sleep_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -369,16 +359,6 @@ }; big_cpu_sleep_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <549>; - exit-latency-us = <901>; - min-residency-us = <1774>; - local-timer-stop; - }; - - big_cpu_sleep_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -721,49 +701,49 @@ cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>; }; cluster_pd0: power-domain-cluster0 {