diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml index 3c5305b688ec7..1774a4511c8f4 100644 --- a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml @@ -15,7 +15,11 @@ description: properties: compatible: - const: qcom,glymur-iris + oneOf: + - items: + - const: qcom,nord-iris + - const: qcom,glymur-iris + - const: qcom,glymur-iris clocks: maxItems: 9 diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index 0d1c561b1f9e0..6d08b829681d3 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -1242,6 +1242,115 @@ #power-domain-cells = <1>; }; + iris: video-codec@aa00000 { + compatible = "qcom,nord-iris", "qcom,glymur-iris"; + reg = <0x0 0x0aa00000 0x0 0x000f0000>; + + clocks = <&nwgcc NW_GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, + <&nwgcc NW_GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS1_CLK>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun", + "iface2", + "vcodec1_core", + "vcodec1_core_freerun"; + + dma-coherent; + + interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = ; + + iommus = <&apps_smmu_1 0x0960 0x0020>, /* Video VM0 XTENSA non-secure non-pixel */ + <&apps_smmu_1 0x0943 0x0000>, /* Video VM0 VCODEC non-secure pixel */ + <&apps_smmu_1 0x0944 0x0000>, /* Video VM0 VCODEC non-secure bitstream */ + <&apps_smmu_1 0x0940 0x0020>; /* Video VM0 VCODEC non-secure non-pixel */ + + memory-region = <&video_mem>; + + operating-points-v2 = <&iris_opp_table>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc VIDEO_CC_MVS1_GDSC>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx", + "vcodec1"; + + resets = <&nwgcc NW_GCC_VIDEO_AXI0_CLK_ARES>, + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, + <&nwgcc NW_GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core", + "bus2", + "vcodec1_core"; + + /* + * IRIS firmware is signed by vendors, only + * enable on boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 240000000 360000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-435000000 { + opp-hz = /bits/ 64 <435000000 435000000 652500000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000 480000000 720000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333333 { + opp-hz = /bits/ 64 <533333333 533333333 800000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000 560000000 840000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,nord-videocc"; reg = <0x0 0x0aaf0000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/qcom/nord-ride-sx.dts b/arch/arm64/boot/dts/qcom/nord-ride-sx.dts index b8839e1b86421..77100338ad447 100644 --- a/arch/arm64/boot/dts/qcom/nord-ride-sx.dts +++ b/arch/arm64/boot/dts/qcom/nord-ride-sx.dts @@ -569,6 +569,12 @@ status = "okay"; }; +&iris { + firmware-name = "qcom/vpu/vpu36_p4_s7.mbn"; + + status = "okay"; +}; + &qupv3_0 { firmware-name = "qcom/nord/qupv3fw.elf"; diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qcom/nord-rrd.dts index ddc534e2214b4..62b60d669cb7d 100644 --- a/arch/arm64/boot/dts/qcom/nord-rrd.dts +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -521,6 +521,12 @@ }; }; +&iris { + firmware-name = "qcom/vpu/vpu36_p4_s7.mbn"; + + status = "okay"; +}; + &qupv3_0 { firmware-name = "qcom/nord/qupv3fw.elf"; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c index ca03d65705136..dbc5e581a0cad 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -3,6 +3,8 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + #include "iris_instance.h" #include "iris_vpu_buffer.h" #include "iris_hfi_gen1_defines.h" @@ -1808,6 +1810,10 @@ u32 hfi_buffer_dpb_enc_ar50lt(u32 frame_width, u32 frame_height, bool is_ten_bit static u32 iris_vpu_enc_arp_size(struct iris_inst *inst) { + /* TODO: remove once firmware no longer needs 2x ARP size on Nord */ + if (of_device_is_compatible(inst->core->dev->of_node, "qcom,nord-iris")) + return 2 * HFI_BUFFER_ARP_ENC; + return HFI_BUFFER_ARP_ENC; } diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 01dca97e26714..f1dae46f1b585 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -259,6 +259,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,msm8976", .data = &no_ubwc_data }, { .compatible = "qcom,msm8996", .data = &msm8998_data }, { .compatible = "qcom,msm8998", .data = &msm8998_data }, + { .compatible = "qcom,nord", .data = &glymur_data }, { .compatible = "qcom,qcm2290", .data = &qcm2290_data, }, { .compatible = "qcom,qcm6490", .data = &sc7280_data, }, { .compatible = "qcom,qcs8300", .data = &sc8280xp_data, },